Generally, semiconductor devices are formed by alternately stacking layers of conducting and insulating materials over a semiconductor substrate. Contact holes are etched through some or all of these layers at specific locations and, thereafter, metal conductors are deposited into the holes to provide for electrical contact to external circuits. Contact holes are typically etched down to active areas on the surface of the substrate or to an intervening conductive layer. Variations in the thickness of the layers of material, non-uniformity of the film deposition and planarizing processes and limitations inherent in the etching process make it difficult to ensure the contact hole will stop precisely on the conductive layer to which contact will be made. This is particularly true as the conductive layers are made thinner for the increasingly small memory cell components currently being incorporated into random access semiconductor memory devices. Where contact must be made to a conductive layer that is thin in comparison to the overlaying materials through which the contact hole is etched, the contact hole etch must be precisely controlled to maximize the chances the hole stops on the thin conductive layer.
The problems associated with forming reliable contacts to a thin conductive layer are illustrated below where I have described part of a process for manufacturing a conventional stacked capacitor DRAM. FIG. 1 shows the structure of a conventional stacked capacitor DRAM after formation of the capacitor top electrode, also commonly referred to as the “cell poly.” Cell poly 2 is a layer of doped polysilicon formed over dielectric layer 4, capacitor bottom electrode 6, field effect transistor gate electrode 8, and substrate 10.
Referring to FIG. 2, upper insulating layer 12 is stacked over substrate 10. Upper insulating layer 12 is etched to form a contact hole 14 which, ideally, extends just down to cell poly 2. In order to minimize the number of manufacturing process steps, this contact hole etch is typically performed as part of the same etch that forms bit line contact 15. Contact hole 14 is then filled with a metal conductor 16 for electrically connecting the cell poly to an external voltage source.
Upper insulating layer 12 and cell poly 2 are typically about 20,000 Angstroms and 1,000 Angstroms thick, respectively. The thickness of upper insulating layer 12 may vary from place to place due to the stepped substrate materials over which it is formed and non-uniformity of the film deposition and planarizing processes. Also, the contact hole etch must continue long enough to expose the deepest contact, bit line contact 15 in this example, at the thickest part of upper insulating layer 12. Hence, the contact hole will be over etched into and sometimes through the thin cell poly as illustrated in FIG. 3A. Etching through cell poly 2 diminishes the effectiveness of the cell poly/metal contact by forming a sidewall contact causing undesirable high contact resistance between conductor 16 and cell poly 2. Where the cell poly is formed in close proximity to the substrate, as shown in FIG. 3B, etching through cell poly 2 causes electrical shorting of cell poly 2 to substrate 10 through conductor 16.
Current methods to reduce the risk of over etching the cell poly contact hole include precisely controlled etch times and the development and use of highly selectively etch processes. Adequate selectivity is difficult to achieve, however, as device geometries shrink, bit line contacts become deeper and the cell poly becomes thinner.
One solution to the problem of shorting a thin conductive layer (described above for the cell poly) is disclosed in U.S. Pat. No. 5,243,219, issued to Katayama on Sep. 7, 1993. Katayama discloses an impurity diffused region in the substrate directly below the contact hole. The resulting pn junction between the impurity diffused region and the substrate isolates the conductive layer from the substrate in the event the contact hole is etched through the thin conductive layer. Although the device of Katayama minimizes some of the undesirable effects of etching through the thin conductive layer, it does not eliminate this fundamental problem which is inherent in the formation of reliable contacts to a thin conductive layer.
There remains a need for a structure and manufacturing process that lessens or eliminates the risk of etching the contact hole through a thin conductive layer. It is desirable that such structure and process be of practical use in a variety of semiconductor device applications, including those in which the conductive layer is remote from the substrate.